The present invention concerns security protection within an integrated circuit design and pertains particularly to power-on-reset logic with secure power down capability.
For some processing applications, it is essential to operate in a secure environment so that operations cannot be probed or altered. In the prior art, various methods have been used to provide for a secure processing environment.
A power-on-reset cell provides a known state for a device when power is applied. Initializing to a known state is critical to a secure processor chip. This is used to ensure the initial state of the processing chip is always defined. Therefore, the integrity of the power-on-reset cell is imperative for the security of the system.
However, there are test strategies that require that all elements of an integrated circuit to be powered down into a low power state to test the chip at time of manufacture (called IDDQ testing). Since during IDDQ testing the state of any register or information on the integrated circuit cannot be defined at power-on time, it is desirable to place the power-on-reset cell into a power-down state in order to allow testing.
However if an external pin is used to power down the power-on-reset cell, the external pin could potentially be used by an attacker to bypass the power-on-reset cell and bring the integrated circuit up into an undefined initial state. It is desirable, therefore, to find a way to allow a power-on-reset cell to be powered down for testing while assuring that the power-on-reset feature of the integrated circuit cannot be bypassed by an attacker.